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Creating SystemVerilog like interface in SystemC : Part 1 by azarmadr3

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· @azarmadr3 ·
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Creating SystemVerilog like interface in SystemC : Part 1
#### Disclaimer(lol):I haven't tested this yet, hoping this works
# Interface in SystemC
![image.png](https://images.ecency.com/DQmcXG8FPscAmy6PAXSYyB3r68GLjPjy6wwZmpK18f5KHp8/image.png)
## Connections in Driver or Monitor
### Driver
![image.png](https://images.ecency.com/DQmSyViScyvx2CJqcxy3GdM7s1YXLXsPq4FoNam98iFkq4i/image.png)![image.png](https://images.ecency.com/DQmPwXM1KufVuNEy5b4GLmsZ1Ac3cPA4XnRAEbBpDZdFYuP/image.png)
### Monitor
![image.png](https://images.ecency.com/DQmYZkyFvRgb16E5snbNtykZuiZQd1RXtULSbH9Qc787Mnj/image.png)![image.png](https://images.ecency.com/DQmZTx9gaULgSerAPPCdtLUbNQSMTN1fsef6x1aY7CU2g8Q/image.png)
Next part contains how to connect in agent, testbench and sc_main.
👍  , , , , ,
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vote details (6)
@gitplait-mod1 ·
Thanks for sharing your work on C  with us. I hope it will work for you. We are looking for people like you in our community. 

 <sub> Your post has been submitted to be curated with @gitplait community account because this is the kind of publications we like to see in our community. </sub>

Join our [Community on Hive](https://hive.blog)
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