RE: Logic Design - How to write simple RAM in VHDL by drsensor

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voter

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wgt%

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drifter1

0 B

19,485,224,300

100%

@drifter1 · Jun 4 '18

$0.07

Oh no you got me!

I'm thinking of implementing something "big" that will of course contain a State machine (FSM) and will then be uploaded to a Xilinx FPGA (I will buy a relatively good one in the Summer).

So, be prepared! More is yet to come!
This is just the beginning :D

👍 drifter1, drsensor

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