RE: Logic Design - How to write simple RAM in VHDL by dexterdev

vhdl · @dexterdev · May 30 '18

$0.08

You reminded me my M Tech days. I used to struggle with VHDL. Its nice to see these topics in steemit. I will wait for more similar stuff. Maybe you can upload your codes in github too. :)

👍 drifter1

`author`	dexterdev
`permlink`	re-drifter1-logic-design-how-to-write-simple-ram-in-vhdl-20180530t090539813z
`category`	vhdl
`json_metadata`	{"tags":["vhdl"],"app":"steemit/0.1"}
`created`	2018-05-30 09:05:42
`last_update`	2018-05-30 09:05:42
`depth`	1
`children`	1
`last_payout`	2018-06-06 09:05:42
`cashout_time`	1969-12-31 23:59:59
`total_payout_value`	0.061 HBD
`curator_payout_value`	0.014 HBD
`pending_payout_value`	0.000 HBD
`promoted`	0.000 HBD
`body_length`	188
`author_reputation`	17,771,704,061,240
`root_title`	"Logic Design - How to write simple RAM in VHDL"
`beneficiaries`	`[]`
`max_accepted_payout`	1,000,000.000 HBD
`percent_hbd`	10,000
`post_id`	58,412,063
`net_rshares`	20,288,727,775
`author_curate_reward`	""

properties (23)vote details (1)

voter	weight	wgt%	rshares	pct	time
drifter1	0 B		20,288,727,775	100%

`author`	drifter1
`permlink`	re-dexterdev-re-drifter1-logic-design-how-to-write-simple-ram-in-vhdl-20180530t093258964z
`category`	vhdl
`json_metadata`	{"tags":["vhdl"],"app":"steemit/0.1"}
`created`	2018-05-30 09:33:03
`last_update`	2018-05-30 09:33:03
`depth`	2
`children`	0
`last_payout`	2018-06-06 09:33:03
`cashout_time`	1969-12-31 23:59:59
`total_payout_value`	0.056 HBD
`curator_payout_value`	0.016 HBD
`pending_payout_value`	0.000 HBD
`promoted`	0.000 HBD
`body_length`	146
`author_reputation`	98,202,866,830,354
`root_title`	"Logic Design - How to write simple RAM in VHDL"
`beneficiaries`	`[]`
`max_accepted_payout`	1,000,000.000 HBD
`percent_hbd`	10,000
`post_id`	58,414,965
`net_rshares`	19,447,744,241
`author_curate_reward`	""

voter	weight	wgt%	rshares	pct	time
drifter1	0 B		19,447,744,241	100%

voter

weight

wgt%

rshares

pct

time

drifter1

0 B

19,447,744,241

100%