Viewing a response to: @dexterdev/re-drifter1-logic-design-how-to-write-simple-ram-in-vhdl-20180530t090539813z
I plan to make something more advanced in the near future! I will keep github in mind, but I guess it will just be a small series here on steemit!
| author | drifter1 |
|---|---|
| permlink | re-dexterdev-re-drifter1-logic-design-how-to-write-simple-ram-in-vhdl-20180530t093258964z |
| category | vhdl |
| json_metadata | {"tags":["vhdl"],"app":"steemit/0.1"} |
| created | 2018-05-30 09:33:03 |
| last_update | 2018-05-30 09:33:03 |
| depth | 2 |
| children | 0 |
| last_payout | 2018-06-06 09:33:03 |
| cashout_time | 1969-12-31 23:59:59 |
| total_payout_value | 0.056 HBD |
| curator_payout_value | 0.016 HBD |
| pending_payout_value | 0.000 HBD |
| promoted | 0.000 HBD |
| body_length | 146 |
| author_reputation | 98,202,866,830,354 |
| root_title | "Logic Design - How to write simple RAM in VHDL" |
| beneficiaries | [] |
| max_accepted_payout | 1,000,000.000 HBD |
| percent_hbd | 10,000 |
| post_id | 58,414,965 |
| net_rshares | 19,447,744,241 |
| author_curate_reward | "" |
| voter | weight | wgt% | rshares | pct | time |
|---|---|---|---|---|---|
| drifter1 | 0 | 19,447,744,241 | 100% |
hiveblocks